
Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems
The aim of the Design Flows and System Design area of APECS is to simplify the design process of chiplet-based systems by providing basic chiplet IPs. Chiplets are modular, reusable hardware IPs that are used as building blocks in complex systems. They enable the integration of different functions and technologies in a single system. Chiplets can provide different functions such as processors, memory, RF components or sensors and offer flexibility in system design. By using chiplets, different technologies can be combined to utilize the best features of each technology, resulting in improved performance and efficiency.
APECS focuses on System Technology Co-Optimization (STCO) for system design. System Technology Co-Optimization is a methodology that aims to improve the interaction between different design aspects. Not only individual components are considered, but also their influence on the entire system. The consideration of cross-references and repercussions between design and technological implementation leads to a holistic view. This accelerates the development process and makes it more efficient.
Within the area of “Design Flows and System Design” in APECS, we deal with the design for quasi-monolithic integration.
We focus on the implementation of functional safety requirements when modeling IP cores with the help of a functional safety design flow. As an example, we will implement this on our RISC-V and TSN-IP cores. We will draw on our many years of experience in the area of “Safety by Design” and the functional safety features of our IP cores.