APECS Pilot Line: Demos & Application Solutions

The demonstrator shows how modern HPC system modules can be implemented in real applications. It provides a platform for the demonstration and further development of hybrid packaging solutions in electronics. The demonstrator is based on a silicon interposer equipped with several computing and acceleration units as well as high bandwidth memory (HBM). The use of hybrid bonding and high-density interposers enables the integration of more than 5 chiplets. It thus represents an important step in the integration of high-performance computing (HPC) and artificial intelligence (AI) in modern electronic systems. Fraunhofer IIS is responsible for the holistic development of the demonstrator.

Contributions of Fraunhofer IPMS to the demonstrator:

We are working on the interposer technology within the demonstrator in close coordination with Fraunhofer IZM-ASSID. Interposers are miniaturized silicon-based circuit boards that electrically connect different chips (e.g. processors, memory). Ultra-high density (UHD) interposers are particularly important for modern applications such as high-performance computing, artificial intelligence and the Internet of Things (IoT), where high processing power and energy efficiency are required.

• Fabrication of various advanced options for interposer UHD-RDL (ultra-high density redistribution layer) with L/S <1 µm, fine pitch interconnects and through-silicon via fabrication at 300 mm wafer level
• Passive components such as capacitors up to 1µF and resistors up to MOhm are integrated into these interposers

Depending on their function, modern sensors are manufactured using different processes and materials (CMOS, post-CMOS, III-V or MEMS). The integration of components from different categories is technologically challenging and often not possible in a single process environment. The demonstrator for a multi-material high-performance sensor system therefore shows the capabilities of the APECS pilot line in the areas of design, processing and integration of modular, high-performance sensor systems.

The demonstrator combines multi-material sensor chiplets with heterogeneous system interposers and advanced sensor front-ends. In addition, neuromorphic accelerators can be integrated to achieve maximum energy efficiency and low latency. This combination of technologies enables the development of versatile and intelligent sensor systems that are suitable for a wide range of applications. Fraunhofer ISIT is responsible for the overall development of the demonstrator.

Contributions of Fraunhofer IPMS to the demonstrator

• Development of a generic accelerator interface for integration in various sensor applications
• Development of a QMI-integrated acoustic sensor chiplet

Three demonstrators will be set up to show the capabilities of the APECS pilot line in the area of RF integration. These will combine different chiplets. Chiplets are modular, reusable hardware IPs that are used as building blocks in complex systems. They enable the integration of different functions and technologies in a single system.

The following chiplets are combined in the demonstrators:

• InP chiplets on SiGe-BiCMOS
• mHEMT H-band LNA chiplets
• SiGe-BiCMOS mixed-signal chiplets

The chiplets are specially adapted for use in radar modules. The Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik is responsible for the development of the integrated demonstrators.

Contributions of the Fraunhofer IPMS to the demonstrator

We are part of the SiGe-BiCMOS mixed-signal chiplets demonstrator: a D-band radar transceiver module with a BiCMOS radar chiplet and an RF glass interposer with attached antenna structures.

• Chiplets for a D-band communication interface of a radar chiplet and a radar module are each adapted and optimized on schematic and layout level to be integrated in a fan-out wafer level packaging.
• Chiplets with a 22nm FDSOI-CMOS semiconductor technology for ADC (analog digital converter)