Fraunhofer Institute for Photonic Microsystems
Fraunhofer Institute for Photonic Microsystems

Nanopatterning / Lithography

300 mm CMOS Cleanroom

Nanopatterning / E-Beam Lithography

Nanopatterning / E-Beam Lithography

© Fraunhofer IPMS
E-Beam Lithography area in 300 mm CMOS Clearoom at Fraunhofer IPMS.
© Fraunhofer IPMS
TEL Etch tool in 300 mm CMOS Clearoom at Fraunhofer IPMS.

Creating nano-scale structures is crucial for a wide range of applications in the semiconductor business. Key challenges are creating precisely controlled patterns with small dimensions, flexible and adaptable layout generation and processes as well as uniform and reproducible wafer-scale integration.

Fraunhofer IPMS offers state-of-the-art nanopatterning capabilities using electron beam direct write lithography and reactive ion etching. Thus, customized structures with sizes below 40 nm can be created on a variety of wafer sizes and substrate types. Starting from the customer’s design the whole package involving layout generation and modification, data preparation, e-beam lithography, pattern transfer using etch processes together with the in-line metrology and analytics up to dicing into single chips is offered.

 

Application examples

  • Fabrication of test structures for technology development
  • Structuring of Application Specific Integrated Circuits (ASICS)
  • Design tests of innovative devices and cell concepts and their variation on a wafer (Chip Shuttle)
  • Calibration pattern for metrology development
  • MEMS and NEMS patterning with productive quality
  • “Mix & Match” with optical exposure techniques

E-Beam Lithography as key enabling process to reach sub 80 nm structures for Quantum Computing applications in CMOS Fab environment

© Fraunhofer IPMS
Parameters of the process stability on 300 mm wafers - pattern fidelity, uniformity and wafer to wafer reproducibility. Distribution of a 100 nm trench width with pitch 1/1 measured with CD-SEM over the 300 mm wafer

Universal quantum computers promise the possibility of solving certain computational problems significantly faster than classically possible. For relevant problems, millions of qubits are needed, which is only feasible with industrial production methods. This study presents an electron beam patterning process of gate electrodes for Si/SiGe electron spin qubits, which is compatible with modern CMOS semiconductor manufacturing. Using a pCAR e-beam resist, a process window is determined in which structure sizes of 50 nm line and 30 nm space can be reproducibly fabricated with reasonable throughput. Based on electrostatic simulations, we implemented a feedback loop to investigate the functionality of the gate electrode geometry under fabrication-induced variations.

Publication: Proceedings Volume 12802, 38th European Mask and Lithography Conference (EMLC 2023)

Publications Lithography:

Publications Etch and Metrology:

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