
Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems
An important part of APECS is 2.5 and 3D integration technologies, which are crucial for creating powerful, compact and energy-efficient systems. 2.5D integration combines the advantages of 2D and 3D technologies by placing multiple chips in a single plane connected by an interposer layer. This technique enables optimal connection and communication between the chips, improves signal quality and reduces latency. As a result, different technologies and materials can be combined efficiently, which increases the flexibility and performance of the systems. 3D integration goes one step further and stacks chips vertically, resulting in even shorter wiring connections. This arrangement allows for a significant improvement in data transfer rates and overall performance while minimizing space requirements. The reduction in signal paths also contributes to energy efficiency, which is of great importance in high-performance applications.
Within APECS, we are developing technologies for 2.5D and 3D integration at 300 mm wafer level in close cooperation with Fraunhofer IZM-ASSID. The aim is to enable 3D stacking of advanced CMOS wafers and non-CMOS heterogeneous/multi-material wafers. In 2.5D integration, chiplets are to be integrated directly onto interposers. These developments are particularly important for applications in the fields of neuromorphic computing, trusted electronics (e.g. security functions) and are the basis for integrated high-performance chips.
See more on each topic below.
We are researching UHD interposers, which are characterized by high density, good thermal management and high integration capability. Interposers are miniaturized silicon-based printed circuit boards that electrically connect different chips (e.g. processors, memory). UHD interposers are particularly important for modern applications such as high-performance computing, artificial intelligence and the Internet of Things (IoT), where high processing power and energy efficiency are required.
Advantages of UHD interposers:
Our UHD interposers are designed to achieve the following performances:
We are researching passive functionalized interposers. They are used to integrate various functional features required for a complex system already in the printed circuit board, but without containing active electronic components (as these are then supplied by the chiplets). These interposers serve as connecting elements between different chips and enable communication and data exchange between them. Passive functional interposers are often used in high-performance applications, in data processing, in the Internet of Things (IoT) and in telecommunications, where reliable connection and signal processing as well as strong miniaturization are required.
Benefits:
Our research topics in this area:
We are exploring the use of RDL (Redistribution Layers) for 3D integration.
The goal is to enable 3D stacking of advanced CMOS wafers and non-CMOS heterogeneous/multi-material wafers. These technologies offer increased performance, efficiency, and flexibility.
Advantages of 3D integration with additional RDL: