APECS Pilot Line: Chiplet Integration (2.5D and 3D)

Chiplet integration (2.5D and 3D)

Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems

An important part of APECS is 2.5 and 3D integration technologies, which are crucial for creating powerful, compact and energy-efficient systems. 2.5D integration combines the advantages of 2D and 3D technologies by placing multiple chips in a single plane connected by an interposer layer. This technique enables optimal connection and communication between the chips, improves signal quality and reduces latency. As a result, different technologies and materials can be combined efficiently, which increases the flexibility and performance of the systems. 3D integration goes one step further and stacks chips vertically, resulting in even shorter wiring connections. This arrangement allows for a significant improvement in data transfer rates and overall performance while minimizing space requirements. The reduction in signal paths also contributes to energy efficiency, which is of great importance in high-performance applications.

Fraunhofer IPMS in APECS: Chiplet integration platform (2.5D and 3D)

Within APECS, we are developing technologies for 2.5D and 3D integration at 300 mm wafer level in close cooperation with Fraunhofer IZM-ASSID. The aim is to enable 3D stacking of advanced CMOS wafers and non-CMOS heterogeneous/multi-material wafers. In 2.5D integration, chiplets are to be integrated directly onto interposers. These developments are particularly important for applications in the fields of neuromorphic computing, trusted electronics (e.g. security functions) and are the basis for integrated high-performance chips.

Our research topics in the field of 2.5D and 3D chiplet integration platforms:

  • Ultra-High-Density (UHD) interposers
  • Passive functionalized interposers
  • 3D stack integration

See more on each topic below.

Ultra-high density (UHD) interposer

We are researching UHD interposers, which are characterized by high density, good thermal management and high integration capability. Interposers are miniaturized silicon-based printed circuit boards that electrically connect different chips (e.g. processors, memory). UHD interposers are particularly important for modern applications such as high-performance computing, artificial intelligence and the Internet of Things (IoT), where high processing power and energy efficiency are required.

Advantages of UHD interposers:

  • High density: UHD interposers offer an extremely high density of wiring points, which makes it possible to connect chips with high I/O density (the latest chip generations).
  • Versatility: They support different technologies and components such as MEMS, optical devices and RF (radio frequency), allowing complex systems to be built.
  • Thermal management: UHD interposers will also offer integrated cooling solutions to optimize heat dissipation in high-performance applications.
  • Integration: They enable the simultaneous integration of different chip technologies in a single packaging process flow, making production more efficient.

Our UHD interposers are designed to achieve the following performances:

  • High aspect ratios of TSVs (Through Silicon Via) of 20:1 with scaled CD (Critical Dimension) <500 nm 
  • Wiring planes with line/space (L/S) structures up to 200 nm 
  • Research on low TRL: 30 nm vias and <100 nm L/S 

Passive functionalized interposer

© Fraunhofer IPMS
Functional interposer with wiring level

We are researching passive functionalized interposers. They are used to integrate various functional features required for a complex system already in the printed circuit board, but without containing active electronic components (as these are then supplied by the chiplets). These interposers serve as connecting elements between different chips and enable communication and data exchange between them. Passive functional interposers are often used in high-performance applications, in data processing, in the Internet of Things (IoT) and in telecommunications, where reliable connection and signal processing as well as strong miniaturization are required.

Benefits:

  • Improved signal quality: by integrating passive components, signal distortion and noise can be reduced, resulting in better overall performance.
  • Increased functionality: Functionalization enables additional features such as integrated sensors or cooling mechanisms that extend the functionality of the system.
  • Compactness: Passive interposers enable the integration of several technologies in a compact area, which saves space in the overall design. Furthermore, additional discrete components can be dispensed with, which helps to minimize the size of the overall system.
  • Flexibility: They support the combination of different technologies and components, which increases adaptability to different applications.
  • Cost efficiency: By reducing the number of active components required, production costs can be lowered while improving system performance.
  • Easy integration: Passive functionalized interposers facilitate the connection between different chips and technologies, simplifying the manufacturing and design of complex systems.

Our research topics in this area:

  • Integrated passive components (high-density capacitors, resistors) 
  • Integrated waveguides (nanoscale silicon nitride (SiN))
  • Embedded cooling technologies

3D stack integration

We are exploring the use of RDL (Redistribution Layers) for 3D integration.
The goal is to enable 3D stacking of advanced CMOS wafers and non-CMOS heterogeneous/multi-material wafers. These technologies offer increased performance, efficiency, and flexibility.

Advantages of 3D integration with additional RDL:

  • Enabling new architectures:
    The implementation of novel chip architectures, such as 3D ICs where multiple chips are vertically stacked, becomes possible. This architecture can significantly boost performance and increase communication bandwidth.
  • Space optimization:
    RDL allows for more efficient use of available wafer area by rerouting interconnections. This is particularly important for the miniaturization of components.
  • Improved signal transmission: RDL enables shorter and optimized signal paths, which improves signal quality and reduces signal delay—critical for high-speed applications.
  • Design flexibility: RDL provides designers with greater flexibility in placing components and connections, facilitating the development of complex and high-performance systems.
  • Energy efficiency: By optimizing signal paths, energy losses can be minimized, leading to an overall more energy-efficient design.
  • Scalability: RDL technology is scalable and supports the development of future technologies in the sub-100 nm range—crucial for continued miniaturization in microelectronics

Further information:

 

Fraunhofer IPMS

300 mm CMOS Cleanroom