International Conference on IC Design and Technology 2021

Tutorials are about 1.5 hours long with additional discussion time. Tutorials will take place on Wednesday, September 15, 2021 and can be booked optionally in addition to the conference. Please click the registration tab for more info. 

The tutorials each consist of a 60 min lecture and 30 min Q&A.

For more information about the tutorials please scroll down!

An underestimated design related product reliability risk from plasma processing induced charging damage - PID

Plasma processing induced charging damage (PID) is a serious reliability risk for designs of integrated circuits of various processing nodes and several device types. Dependent on the type/style of design the sensitivity to PID can vary significantly. The most prominent degradation is reported for MOS transistors, but also integrated capacitors can suffer degradation or even dielectrics between metal lines in the metal stack. Any type of technology can be affected implemented on bulk-silicon or on SOI with dielectrics such as SiO₂ as well as high-K materials. The reliability risk for a productive circuit is supposedly eliminated by so-called antenna design rules. The maximum metal area causing the charging event is limited in the design manual. However the antenna design rules are only sufficient when the PID reliability stress characterization throughout the process qualification has a high grade and is complete. The incorporation of all possible degradation modes for the PID failure mechanism is essential but not necessarily accomplished. The open question is: “Are all PID risks covered by the rules in the design manual?”

In this tutorial the PID-basics such as antenna ratio, electron shading effect etc. are described briefly and furthermore pitfalls and new findings are highlighted, which could cause significant product risks depending on the layout style. An important topic are the protective devices against PID, their effectiveness is discussed. Aspects associated with 3D-systems are illustrated with respect to PID. Also the limitations of design rule checkers and circuit routing tools are described. The tutorial will give the “beginner” an introduction to the PID-topic while the advanced scientists gets a further perspective into the more or less hidden problem areas.

• Download information for tutorial #1

GaN Power Devices: From Technology to Reliability Challenges

GaN power devices have excellent properties for application in the power conversion field. The wide bandgap, the high sheet channel density, the large breakdown field permit to substantially increase performance and reduce losses, compared to conventional silicon devices. Different device structures are available, from lateral normally-off transistors, to fully vertical device architectures. This tutorial reviews the main properties of gallium nitride, and the unique characteristics of GaN-based devices. Details on lateral and vertical device architectures will be given, to present a comprehensive overview on the topic.

In the second part of the presentation, the main reliability challenges for GaN devices will be discussed, with focus on dynamic on-resistance and breakdown phenomena. Finally, perspectives in the GaN field will be presented.

• Download information for tutorial #2

Neuromorphic Computing for Edge AI

Neuromorphic Computing Technology is a brain-inspired sensing and processing hardware for more efficient and adaptive computing. It promises energy-efficient implementation of human cognition, such as interpretation and autonomous adaptation. Although the communication pathways in the brain and other neural systems cannot be directly translated into electronic circuits, these mathematical models provide the basis for the implementation. Various hardware realizations are currently discussed such as:  mixed-signal analog/digital CMOS circuits, asynchronous event-based communication and processing schemes as well as memristive, phase-change, ferroelectric or spintronic devices, and other nano-technologies. In this tutorial we will introduce these realizations and discuss merits and challenges to reach the goal for efficient neuromorphic computing hardware for edge intelligence systems.

• Download information for tutorial #3

Large-Scale Silicon Photonic MEMS Switches 

Silicon photonics has emerged as a promising solution to address the interconnect bottleneck in high performance computing systems and data centers. Silicon photonics provides unprecedented I/O bandwidth, enabling ultrahigh aggregated bandwidth (~ 10 Tbps), high bandwidth density (~ Tbps/mm), and high energy efficiency (~ pJ/bit). In addition, silicon photonics also enable optical switching with large port count and short switching time.

This talk will provide an overview of the state of the art of silicon photonic switches, with emphasis on new micro-electro-mechanical-system (MEMS)-actuated switching mechanism. Large scale (240x240) switches have been demonstrated, as well as wavelength-selective switches with 8x8 ports and 8 wavelengths.

Future scaling to even larger port count will be discussed.

• Download information for tutorial #4

Dr. Abu Sebastian - IBM Research (Zurich, Switzerland)

"In-memory computing: The next frontier in deep learning acceleration?"

The rise of AI and in particular deep learning is a key driver for innovations in computing systems. There is a significant effort towards the design of custom ASICs based on reduced precision arithmetic and highly optimized dataflow. However, the need to shuttle millions of synaptic weight values between the memory and processing units, remains unaddressed. In-memory computing (IMC) is an emerging computing paradigm that addresses this challenge of processor-memory dichotomy. Attributes such as synaptic efficacy and plasticity can be implemented in place by exploiting the physical attributes of memory devices such as phase-change memory (PCM). It is shown that, using custom “additive noise training”, software equivalent accuracy deep learning inference is possible. Moreover, using a mixed-precision training approach, iso-accuracy training is also possible. The IMC approach can be easily extended to spiking neural networks and to also implement additional entities such as explicit associative memory in an efficient manner for memory augmented neural networks. I will also present deep learning demonstrations based on a first of its kind IMC compute core based on PCM integrated in 14nm CMOS technology. Finally, I will provide a brief overview of photonic in-memory computing that could facilitate unprecedented latency and compute density.

• Download abstract and short bio

Dr. Chidi Chidambaram - Qualcomm (Albany, New York, US)

"Semiconductor challenges in realizing the full benefit of  5G mmWave and extending the roadmap into 6G"

Chidi Chidambaram leads the process technology and foundry engineering team at Qualcomm as Vice President Engineering. Qualcomm is a leader among the fab less industry in bringing leading edge semiconductor technologies to manufacturing - Qualcomm was the first company to ship large volume products in 10 nm technology in 2017. Chidi’s team is also responsible for RF devices based on finlet and SOI transistors. Earlier Chidi developed silicon technology at Texas Instruments and was instrumental in the first embedded SiGe implementation by semiconductor Industry. Chidi is recognized as a IEEE fellow for contribution to strain engineering and Design technology co-optimization (DTCO).  Chidi’s 20+ year semiconductor career has evenly straddled research and development with over 60 each of refereed articles and patents.

Dr. Mirko Sanzaro - Toshiba Europe / Cambridge Research Laboratory (UK)

"A photonic integrated quantum communication system"

Mirko Sanzaro was born in Avola, Italy, in 1988. He received the M.Sc. degree (summa cum laude) in Electronic Engineering and the Ph.D. degree ( summa cum laude) in Information Technology Engineering from Politecnico di Milano, Milan, Italy, in 2013 and 2017, respectively. He is a currently a Research Scientist at Toshiba Europe Limited. His research interests include the design, development, and characterization of Quantum Key Distribution instrumentation.

Dr. Alvin Leng Sun Loke - NXP Semiconductors (San Diego, California, US)

"Driving Automotive ICs into Advanced CMOS"

Alvin Loke is a Technical Director at NXP Semiconductors in San Diego, having worked on every CMOS node spanning from 250nm to 2nm at Agilent, AMD, Qualcomm, and TSMC. He received a B.A.Sc. degree (highest honors) in engineering physics from the University of British Columbia, and M.S. and Ph.D. degrees in electrical engineering from Stanford University. He spent several years in CMOS process integration and has since then worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interfacing, and analog design methodologies. Alvin is an active IEEE Solid-State Circuits Society volunteer, having served as Distinguished Lecturer, Webinar Chair, CICC Committee Member, Denver and San Diego Chapter Chair, and Guest Editor for Journal of Solid-State Circuits and Solid-State Circuits Letters. He currently serves as an AdCom Member and Chapters Chair as well as a VLSI Symposia Committee Member. Alvin has presented many invited talks, including short courses at ISSCC, VLSI Symposia, CICC, and BCICTS. He has authored over 60 publications (including the CICC 2018 Best Paper) and 29 US patents.

Be curious about our social program:

• Networking: Even if we can't meet in person, it's a special concern of ours to get everybody into conversation as known from the past ICICDT events. With our range of networking opportunities everybody can get to know each other and exchange ideas about the latest developments in IC Design and Technology. Take advantage of our lounge room and network easily with other ICICDT attendees.

• Insidertour cleanroom CNT: Be part of a virtual Insidertour through the brandnew clean room of Center Nanoelectronic Technologies CNT which is currently in installation and soon to be ramped up. Learn about the processes and technologies of Fraunhofer IPMS and future developments.

• Dresden city tour: Explore Dresden city during a guided virtual tour with our sympatic Dresden Guide Anett. She will show you all corners, you would have seen in person during a physical event in our beautiful town.

• Photobooth: Also the fun part will not be neglected either. Take a photo of yourself in our virtual photobooth and keep it as a conference souvenir. 

Fraunhofer IPMS

The Fraunhofer Institute for Photonic Microsystems IPMS in Dresden is one of 74 institutes in Germany with a modern R&D infrastructure in the field of optical sensors and actuators, integrated circuits, microsystems (MEMS/MOEMS) and nanoelectronics. Fraunhofer IPMS is a worldwide leader in research and development services for electronic and photonic microsystems in the fields of Smart Industrial Solutions, Medical & Health applications and Improved Quality of Life. Innovative products can be found in all large markets – such as ICT, consumer products, automobile technology, semiconductor technology, measurement and medical technology – products which are based upon various technology developed at Fraunhofer IPMS.

Dresden

We would have loved to welcome you in Dresden, the capital city of the German state of Saxony. Dresden has a long history as the capital and royal residence for the Electors and Kings of Saxony, who for centuries furnished the city with cultural and artistic splendor. The city was known as the Jewel Box, because of its baroque and rococo city centre. Today, Dresden is a cultural, educational and political centre of Germany and Europe. The Dresden University of Technology is one of the 10 largest universities in Germany. The economy of Dresden and its agglomeration is one of the most dynamic in Germany and ranks first in Saxony. It is dominated by high-tech branches, often called “Silicon Saxony”. Dresden is one of the most visited cities in Germany with 4.7 million overnight stays per year. 

ICICDT 2021 allows only online submission of the papers in PDF format. Please strictly follow the guidelines in Author Information while preparing the paper.

It is MANDATORY to verify the PDF file of the paper for IEEE compliance before submission using PDF Express (The conference ID is 51558X.). Papers that are not IEEE compliant will not be included in the proceedings nor published on IEEE Xplore.

When checked with PDF Express the paper is NOT submitted yet. After receiving confirmation of compliance from PDF Express authors must submit the PDF file approved by PDF Express through the online submission system.

Please double check the informations that you provide during online submission:

• title of the paper,
• name, affiliation, e-mail address of the authors,
• name of the corresponding author,
• complete mailing address, phone, fax, and e-mail address of the corresponding author.

Since these informations will be used unchanged in the conference program and proceedings, it is important that you enter them correctly. Please rember to submit online also the IEEE Copyright Form after submitting the final paper.

Invited Speaker

In order to upload your contribution, you would first need to create a user account on ConfTool, our conference management system: https://www.conftool.net/icicdt2021/. After you have done this, we will assign you the status of invited speaker. Once the status is assigned, you will be informed accordingly and you can start uploading your paper. You can submit your contribution by clicking "Your Submissions" on the main page after logging in and then selecting the "Invited Papers" option. Please ignore the "Deadline has passed" information, as an invited speaker this does not apply to you.

When creating your paper, make sure that the following criteria are met:

• Contributions submitted for ICICDT 2021 must be a minimum of two pages and a maximum of four pages, all illustrations and references included.
• The IEEE template is available for download here. Please format your paper according to the manuscript specifications.
• The placeholder for the copyright information at the bottom of the first page must be replaced by the following information: 978-1-6654-4998-4/21/$31.00 ©2021 IEEE.
• Before you upload the final version, the PDF file must pass the IEEE PDF checker. The conference ID is 51558X.
• Please enter a short CV of the presenting author during the upload process.
• When uploading the final camera-ready manuscript, you must indicate whether your paper is a student contribution and grant IEEE Xplore copyright directly via ConfTool.

Please submit your final paper of 2-4 pages on ConfTool by July 15, 2021!
 
Due to the ongoing COVID-19 pandemic, the ICICDT 2021 will be held online. The conference will be an on-demand virtual event of pre-recorded presentations combined with a live event from September 15-17, 2021. We are currently finalizing our agenda and details on the format of the event. Initial information about the program can be found under "Program". Look forward to exciting tutorials, live keynotes and Q&A workshops from September 15 to 17! You can also expect social activities and networking opportunities.

Conference fee
At least one author per paper must be registered for the conference. The early bird price of 255 euros is available until July 15. IEEE members and students are eligible for a discount. For information on ticket prices please click on the registration tab.  Please register for the conference via ConfTool no later than July 15.

Pre-recorded video presentation and summary slide
We kindly ask you to submit a 15-minute video presentation of your work. Taking the participants through your slides in a recorded presentation will allow you to explain your work in greater detail and make it a more personal and engaging experience for the attendees. From the beginning of August you will have access to the event platform where the online conference will take place. There you can then upload your video by yourself. As the presentations are on-demand, not live, you can review and re-record your presentation until you are satisfied with the quality. In addition to the video, please create one summary slide to be used as the basis for the live Q&A workshop sessions. The video presentation and summary templates will be posted online on here soon.

Please prepare and submit your video presentation and summary slide no later than August 25, 2021. This way the videos will be available on-demand to all conference participants one week before the virtual live event.

The conference ID is 51558X.

Our suggested presentation video duration is:

• 10 min for contributed
• 15 min for invited

Create your video

To record your audio, most integrated microphones of notebooks or tablets will be sufficient as long as your recorded speech is clear and easily comprehensible. 

For recording, follow the instructions in our platform help center which you will get access to soon.

Review your video

• Is your file an .mp4, .mpg, .avi, .mov, or .wmv?
  
• Is your audio at the right level, clear, consistent and free from any noises? 
• Does your talk start and end without unnecessary breaks before and after?
• Is there an audio commentary on each slide? Otherwise the correct display duration is not recorded.
• Is everything displayed correctly?

Prepare for questions

While your presentation will be available on demand, there will be a chance for questions and answers in a live session. Please use the Q&A slide template for a summary of your presentation and paper. Please note that the summary should be only one slide. Updated information on the session schedule will be available here in the program section.

Submit your video and summary slide

Presentations for contributed and invited papers can be uploaded to the conference platform in August. Your summary slide can be uploaded there too. Please use .pptx or .ppt file format and, for technical safety, upload the same slide as .pdf. You will receive information on access and a link.