RISC-V Processor IP Core EMSA5-FS for functional safety

Fraunhofer IPMS offers a processor IP core based on the RISC-V architecture, which is certified as ASIL-D ready according to ISO 26262:2018 for functional safety in vehicles. Several IDEs support the EMSA5-FS, enabling efficient and professional development for complete systems, in the context of functional safety according to IEC 61508 and ISO 26262.

The RISC-V IP core can be made available platform-independently for various FPGA platforms and can be integrated into customer-specific ASIC developments for any foundry technologies. Fraunhofer IPMS offers services to extend the processor core IP with customer specific modules and to provide complete subsystems.

Fraunhofer IPMS has more than 20 years of experience in design and licensing of IP cores design with several hundred users worldwide, mainly in the automotive, aerospace and automation industries.

Key Features

• 32-bit, 5-stage pipeline architecture
• AHB-lite interface
• ISO 26262 ASIL-D ready certified
• Integrated redundancy and safety
• Software development according to functional safety IEC 61508 and ISO 26262 with IAR Workbench
• Complete certification package with FMEDA and SAM documents
• Memory protection unit
• ECC protection for busses
• Software test lab (STL)
• MCAL drivers and Complex Device Drivers (CDD)